Very large-scale integration using complementary metal oxide (CMOS) switching elements has long been the main stay of progressive miniaturization. However, energy and scale limits are looming as feature sizes rapidly are approaching the 10nm milestone. Further reduction in size will require novel novel advances for which there are currently no known technological solutions. We are exploring energy-efficient algorithms to mitigate the impact of the limits of charge-based computation as illustrated on the right. Read more here.

Energy Limits in VLSI

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